So the pixel clock is wrong in the driver for 8bit modes. The PLL config is changed from a x5 multiplier to a x6 for 8bit mode. The 10bit mode is at 160MHz, so x6/5 is 192MHz and not 200MHz. Copying the pattern for 10bit which is based on link frequency was erroneous.
The vblank_min values all appear to have come from the downstream driver. Whilst the datasheet gives a TIMING_VTS and TIMING_Y_OUTPUT_SIZE default values that would add up to vblank_min=110, there are no such values provided for 1280x720 or 640x400. I must have thought values worked at some point, but that was a long time ago.
The vblank_min values all appear to have come from the downstream driver. Whilst the datasheet gives a TIMING_VTS and TIMING_Y_OUTPUT_SIZE default values that would add up to vblank_min=110, there are no such values provided for 1280x720 or 640x400. I must have thought values worked at some point, but that was a long time ago.
Statistics: Posted by 6by9 — Tue Dec 23, 2025 1:42 pm