Well, it's hard to abstract such low level stuff, and keep it working in any scenario.
When messing with system clocks, PLL, modules power etc. better be prepared to get you hands dirty.
Those glitches are happening at hardware level, one need to know how they work, or especially how they don't, for Nature cannot be fooled.
And they are documented in chips' datasheets.
BTW, they fixed that clk_peri divider, but only for RP2350![:)]( "Smile")
, at least on paper, never used it though, didn't know it doesn't exist on RP2040, never tried to run UART at 40 baud, but rather at 10 Mbaud.
When messing with system clocks, PLL, modules power etc. better be prepared to get you hands dirty.
Those glitches are happening at hardware level, one need to know how they work, or especially how they don't, for Nature cannot be fooled.
And they are documented in chips' datasheets.
BTW, they fixed that clk_peri divider, but only for RP2350
, at least on paper, never used it though, didn't know it doesn't exist on RP2040, never tried to run UART at 40 baud, but rather at 10 Mbaud.Statistics: Posted by gmx — Sat Dec 13, 2025 12:55 pm