The DMA satisfies the immediate read (with sub-microsecond response time). ARM CPU gets an interrupt informing it of the read, and for a read-sensitive address, updates values in RAM to implement the side-effects.
Ah, OK - that makes more sense. What you had written before implied that reads happened with no CPU interaction at all, and that only writes triggered ARM code to update registers.
Statistics: Posted by raybellis — Tue Aug 05, 2025 2:23 pm