Seeing that the RP1 CFE supports this, I understand that there is no need to modify the rp1-cfe, csi2, or phy drivers. Is my understanding correct that I only need to create the device tree and driver for the PR2100, regardless of whether I use kernel version 6.6.x or 6.12.x?
You mentioned that the RP1 CFE was developed together with the TI 4-input V3Link board. It seems this was developed as part of the upstream Linux standard. Would it be possible for you to share the driver source code and device tree for this?
I have some questions regarding the issues you mentioned:
The PR2100 supports PAL/NTSC/SECAM, and for AHD/PVI/TVI it only supports HD and FHD inputs (among a few other standards). We have already been using it well with virtual channels not only on our ISP but also on other chips. We have register settings and test boards for the bridge chip, but to connect the PR2100 to the RPI5, do we need to configure something called DV timings inside the RPI5?
The PR2100 has a function that allows us to select whether the MIPI output is YUYV or UYVY. We are currently using the RPI5 GPU for color conversion (YUV422 to BGR888). However, due to GPU load, FHD@30fps for a single channel has been the maximum. Therefore, we wanted to offload color conversion via hardware and then perform various image processing tasks on the GPU, so your suggestion was very helpful. If the convert example you mentioned uses a hardware block within the ISP, that would be ideal.
At this point, we’re not even trying to handle 4 streams; we are just trying to receive 2 streams, but it is proving to be quite challenging.
You mentioned that the RP1 CFE was developed together with the TI 4-input V3Link board. It seems this was developed as part of the upstream Linux standard. Would it be possible for you to share the driver source code and device tree for this?
I have some questions regarding the issues you mentioned:
The PR2100 supports PAL/NTSC/SECAM, and for AHD/PVI/TVI it only supports HD and FHD inputs (among a few other standards). We have already been using it well with virtual channels not only on our ISP but also on other chips. We have register settings and test boards for the bridge chip, but to connect the PR2100 to the RPI5, do we need to configure something called DV timings inside the RPI5?
The PR2100 has a function that allows us to select whether the MIPI output is YUYV or UYVY. We are currently using the RPI5 GPU for color conversion (YUV422 to BGR888). However, due to GPU load, FHD@30fps for a single channel has been the maximum. Therefore, we wanted to offload color conversion via hardware and then perform various image processing tasks on the GPU, so your suggestion was very helpful. If the convert example you mentioned uses a hardware block within the ISP, that would be ideal.
At this point, we’re not even trying to handle 4 streams; we are just trying to receive 2 streams, but it is proving to be quite challenging.
Statistics: Posted by stupid dog — Thu Jul 03, 2025 9:06 am