That's exactly what you do.At the very least , I could manage with one ISR if it knows which pin triggered the interrupt but I don't see how that would be available.
There's only one interrupt, but your interrupt handler then looks at the INTR0/INTR1/INTR2/INTR3 registers to see which interrupts are active (or often more useful to look at PROC0_INTS0/1/2/3 so that you only look at the ones that are actually enabled). The SDK provides gpio_get_irq_event_mask() as a wrapper around that register access.
There are separate interrupts (and separate enables) per-CPU, so sometimes you can split the GPIO interrupt handling between the two cores, though that usually only makes sense if you have a completely different purpose that you are using some of the GPIOs for, rather than what you describe here with 6 similar inputs.
Statistics: Posted by arg001 — Sun Aug 04, 2024 3:51 pm